Automated test equipment (ATE) conventionally execute tests on devices such as integrated circuits according to a stored program. In order to diagnose a failure in a device under test (DUT), a number of related stored programs are executed and the results of each of these tests is evaluated. If there is a test program failure in the DUT, the use of multiple tests can narrow down where in the DUT the failure occurred, thereby facilitating further analysis to determine whether a defect is causing the test program failure, and if so what the defect might be.
To aid in the testing process, technologies such as built-in self-test (BIST) can be incorporated into the DUT. As a major portion of the role of ATE migrates from functional testing to structural testing, whereby an action or sequence of actions is taken to place the DUT into a state that enables a particular test, followed by an action or sequence of actions to execute the test, followed by an action or sequence of actions to record the results of the test, and as BISTs become more sophisticated, the relationship between the ATE and the DUT becomes more abstract. That is to say, the ATE simply instructs the BIST to apply a particular test pattern or vector and to report the results. The data developed inside the DUT as a result of executing the test is then scanned out as a bit stream to the ATE. A test program failure, indicating the possibility of a defect in the DUT, is indicated if that data is not what was expected. Adding to the complexity is the fact that there is not a single, standardized way in which data generated by the BIST is communicated to the ATE. Chip designers may use one of several protocols to communicate the data generated by the BIST to the ATE, depending on other design constraints that may need to be considered.
As devices become more complicated, it becomes more difficult to identify where in the DUT is the defect that caused a test program failure. For example, the time at which the defect caused the failure may be separated from the time in which the failure is evidenced in the bit stream. Despite the fact that a relatively large amount of data is being collected, it remains difficult to isolate and pin down the defect.
To summarize, according to the prior art, a planned sequence of tests is applied to a DUT, and the results of those tests are logged and evaluated. If the test results are anomalous, indicating a potential defect in the DUT, further actions can be taken to verify and pinpoint the defect.
The prior art approaches for testing devices are problematic because of the amount of time needed to conduct the sequence of tests and to collect and evaluate the test results before the next step can be taken to pinpoint the cause of a test program failure. A method and/or system that can reduce the length of time needed would be advantageous. The present invention provides a novel solution to this problem and related problems.